Need for frequency detection (in addition to phase detection) in CDRs EditĪ loop filter is inserted between phase comparator and VCO, in CDRs where jitter and noise performances are important (Architectures 2 - 1 and 2 - 2).īoth for architectures 2-1 and 2-2, when high transmission speed is involved, a jitter-out / jitter-in bandwidth of about 1/1000 of the bit rate is specified by most standards. In CDRs instead, the missing transitions of the incoming signal make the frequency comparison with the local clock a more complex affair. On the other hand, synthesizers often require capture ranges well in excess of +/- 25%. A straight forward comparison of the respective cycle period is possible, and effective. In frequency synthesisers the problem of frequency aided acquisition is equally important as in CDRs, but in synthesisers the incoming signal and the local clock are both perfectly periodic waveforms and a phase and frequency detector with a simple architecture can be used. Additional circuitry that can detect the frequency of the incoming data in that range will be adequate, as it will be shown.
#Double edge triggered flip flop wiki free
In practical CDR applications the uncertainty is always contained within ± 25% and in most cases within ±5% (most of this uncertainty comes from the inaccuracy of the VCO free running frequency). Since the uncertainty comes in steps of 100% of f p, an indication of f p with an approximation of +/- 50% is (barely) sufficient. Some additional information about the absolute value of f p is necessary to correctly recover clock and data.